HDL Design House is seeking for experienced engineers to join our team
The ideal candidate will have following skills and background:
- Graduate Computer Science/Electronics
-Good communication skills and ability to succinctly describe design implementations as well as system challenges
-Candidate must have an open mind and an unparalleled ability to learn a new design and new verification methodologies.
-Minimum 3 + years of experience in verification domain
-SystemVerilog/OVM/UVM and “e†(Specman) languages
-Must be proficient with OOP (C++, Java)
-Knowledge of Digital Integrated Circuits
-Knowledge of Hardware Description Languages (VHDL/Verilog)
-Proficient Unix user
-Fluent English is a must
Following skills will be a plus:
-Knowledge of AMBA AHB/AXI, OCP, PCI Express, Ethernet interfaces
-Experience of Verilog, VHDL and scripting languages
-Familiar with scripting tools and languages (e.g. bash, csh, awk, Perl)
-Familiar with development tools (e.g. make and versioning tools (e.g. CVS)
Duties and Responsibilities:
-Implement complete verification solutions using advanced verification methodologies
-Develop or maintain ASIC verification environments to support ASIC development
-Responsible for development and deployment of coverage driven verification methodology
-Responsible for development of SystemVerilog/UVM VIP, constrained random verification environment, test plans and regressions
-Working with design team in all the phases of the verification process to meet quality requirements at block and system level
-Planning and execution of block and system level verification
-Required to use assertions, simulations and debugging on daily basis
-Should be able to comprehend the 'big picture' at the architectural level as well as execute at the detail implementation level
-Proactively collaborate with team members in different locations
For more info please visit : hdl-dh.com or send your application at [email protected]
If you need any aditional information please contact me using Private Messages